| Summary: | 碩士 === 大同大學 === 通訊工程研究所 === 95 === Power management has become a great concern in VLSI design in recent years, this thesis focuses on the improvement of fixed-width multiplier design, by reducing transition or switch. In this paper we present two methods for designing low power error-compensated fixed-width multipliers which keep the input and the output the same bit width. By applying the row-bypassing structure or column-bypassing structure, the columns or rows are passed, and the switching power will be saved. The truncated part that produces the carry-out bits is replaced with several AND gates and OR gates. In other words, given two n-bit inputs, the fixed-width multipliers generate n-bit products with low product error, but use less power when compared with a standard parallel multiplier. A physical implementation of the proposed design used a standard TSMC 0.35 2P4M CMOS process. The multipliers can operate correctly up to 100MHz and supply voltage is 3.3V. Simulation results show that our method has 5% and 13% power reduction and the QSNR improves 10dB.
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