Compiler Optimization to Reduce Cache Power with Victim Cache
碩士 === 國立中正大學 === 資訊工程所 === 96 === This thesis proposes an approach to improve memory hierarchy by reducing miss rate and miss penalty for saving power. a victim cache is added for this purpose. The power consumption is reduced by decreasing the access times to level-2 cache caused by the victim cac...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/42885585653096631889 |