Compiler Optimization to Reduce Cache Power with Victim Cache

• Main Authors: Cheng-yu Lee, 李承諭
• Other Authors: Rong-Guey Chang
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/42885585653096631889

碩士 === 國立中正大學 === 資訊工程所 === 96 === This thesis proposes an approach to improve memory hierarchy by reducing miss rate and miss penalty for saving power. a victim cache is added for this purpose. The power consumption is reduced by decreasing the access times to level-2 cache caused by the victim cache. There are two proposed approaches to improve programs: First, cache block controlling can reduce the unnecessary access. Second, victim cache controlling can make a trade off between L2 cache and victim cache on power. The power and performance is improved with a compiler-control and the miss rate is also reduced. The result that s small and simple cache performs better is shown in the experiment. It can improve about 6.5% of execution time and reduce 32.66% of cache miss and decrease 4.19% of power consumption with 2k direct-mapped cache. The approach is implemented on SUIF and Machine SUIF compiler for the analyzing and inserting the controlling instructions and running on the Wattch simulator.