Compiler Optimization to Reduce Cache Power with Victim Cache
碩士 === 國立中正大學 === 資訊工程所 === 96 === This thesis proposes an approach to improve memory hierarchy by reducing miss rate and miss penalty for saving power. a victim cache is added for this purpose. The power consumption is reduced by decreasing the access times to level-2 cache caused by the victim cac...
Main Authors: | Cheng-yu Lee, 李承諭 |
---|---|
Other Authors: | Rong-Guey Chang |
Format: | Others |
Language: | en_US |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/42885585653096631889 |
Similar Items
-
CACHE MANAGEMENT BY THE COMPILER
by: THABIT, KHALID OMAR
Published: (2007) -
Victim Cache Hit Rate Optimization by using Bookkeeping Mechanisms
by: Chen-Hua Suo, et al. -
Compiler Assisted Cache Prefetch Using Procedure Call Hierarchy
by: Doshi, Sheela A
Published: (2006) -
Compiler Techniques for Transformation Verification, Energy Efficiency and Cache Modeling
by: Bao, Wenlei
Published: (2018) -
Compiler-Enforced Cache Coherence Using a Functional Language
by: Rich Wolski, et al.
Published: (1996-01-01)