Display Controller and Bus Arbiter for VC-1 Codec
碩士 === 國立中正大學 === 電機工程所 === 96 === This report presents two topics – (1) format transformation between 4:2:0 and 4:2:2, and (2) bus arbiter. The Y, Cr and Cb data decoded from the VC-1 decoder belong to the 4:2:0 format, whereas the ADV7321 board only supports the 4:2:2 format in standard definition...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82712793109483291170 |