A Low Power Design of Fast Locking All Digital Phase Locked Loop
碩士 === 國立中正大學 === 電機工程所 === 96 === There is a structures based on time to digital technique with fast locking . We use two step digital oscillator conceptions which are coarse and fine oscillator. The oscillator structures can realize lower power than conventions (Reduce 65% at 500MHz). The fine osc...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/08778552533800827583 |