Design of a FIFO for Data Transfer between Multiple Clock Domains
碩士 === 長庚大學 === 電機工程學研究所 === 96 === In present System-on-Chip(SOC) design, as the wire length and the process difference ,the distribution of a synchronous clock has been a problem . One solution is to use Globally Asynchronous, Locally Synchronous (GALS) to partition the system into several synchro...
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| Format: | Others |
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2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/05799594461902248625 |