Implementation of One-Tap RLS FDE Combined with Viterbi Decoder Using Channel State Information for DSRC Systems
碩士 === 長庚大學 === 電機工程學研究所 === 96 === In this paper, we focus on hardware implementation in FPGA for the receiver of Dedicated Short-Range Communications(DSRC) system. The hardware implementation includes novel one-tap frequency domain equalizer, De-mapping, De-interleaving, Viterbi decoder, and compa...
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| Format: | Others |
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2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/46461324376357000118 |