Investigation of Thermally-Induced Warpage of Package on Package

碩士 === 長庚大學 === 機械工程研究所 === 96 === Package on Package (POP) is popularly accepted in the electronic packaging research, due to the its special features such as separated functional test on top and bottom packages, low cost, and high yield. Because of its multilayer structure, the warpage of packages...

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Bibliographic Details
Main Authors: Po Chen Kuo, 郭柏辰
Other Authors: M. Y. Tsai
Format: Others
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/22753144682736838225
Description
Summary:碩士 === 長庚大學 === 機械工程研究所 === 96 === Package on Package (POP) is popularly accepted in the electronic packaging research, due to the its special features such as separated functional test on top and bottom packages, low cost, and high yield. Because of its multilayer structure, the warpage of packages due to different coefficients of thermal expansion (CTE) will change the stack gap under thermal loading. The gap will yield open and short circuit failures or even lower solder joint reliability. The purposes of this study on POP package are to minimize the bottom package warpage during mold temperature (160℃) to 25℃ and 260℃, and the gap between with top and bottom packages. In this study, The elastic moduli (Es) and CTEs for epoxy molding compound (EMC) and substrate are measured in terms of temperatures by dynamic mechanical analyzer (DMA) and thermal mechanical analyzer (TMA), respectively. A full-field shadow moiré is used for measuring their real-time out-of-plane deformations during heating and cooling conditions. And the finite element method associated with a theory is employed to understand the experiment results. It is found that increasing EMC thickness and CTE or decreasing chip thickness and substrate CTE can reduce the warpage of bottom package, while EMC's CTE just affect the warpage at 25℃ but with slight influence at 260℃ due to the low EMC's elastic module. Regarding the gap between top and bottom packages, increasing EMC thickness and CTE or decreasing chip thickness and substrate CTE can also lower the gap, but within certain range of values.