Simulation of 0.18um Process and Ion Implant for Zener Diode Design
碩士 === 建國科技大學 === 電機工程系暨研究所 === 96 === This research is the Zener Diode design by standard CMOS 0.18m fabricated processes. Only added or modified part of standard processes, the standardized processes could involve the common used Zener Diode, so the SoC(System on one Chip) contains various Zener...
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| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/64481038602168704490 |