Non-destructive Extraction of Inter-Connect Width and Thickness for Nanometer Technology

• Main Authors: Ya-Hui Chen, 陳雅惠
• Other Authors: Tsai-Ming Hsieh
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/33611873869040977576

碩士 === 中原大學 === 資訊工程研究所 === 96 === Semiconductor generation have made great strides from deep sub-micro towards nano-technologies by making great progress in VLSI (Very Large Scale Integration) and advanced processes. It results in reducing interconnect size, adding stack of metal layers, adapting Cu-based technologies, leading into SOC (System on Chip) design concept, and increasing high frequency chip requirement. As a result parasitic effect, ignored in the past but considered due to large number of layers and interconnections, is now the key factor of circuit performance, signal integration, and reliability for IC design. How to evaluate and calculate complex parasitic problems precisely, therefore, will be the difficult challenges. The charge-based capacitance measurement (CBCM) and Kelvin test structure were used for non-destructive extraction of inter-connect width and thickness is demonstrated. Initially, by our electrical-only and non-destructive methodology, an accurate table of width bias or WEE (wire edge enlargement), which is necessary for back-end-of-line (BEOL) design on advanced nanometer technology, can be fully extracted. Secondly, metal and inter-dielectric layer thickness can be extracted by using the equation of parallel capacitance. Finally, we input extract parameters to an analytic formula of capacitance and the value shows better than 5% agreement with the capacitance from the measurement.