Hardware/Software Co-Design FPGA-based Digital Signal Processor with High Area Efficiency

• Main Authors: Yu-Kai Tsai, 蔡玉凱
• Other Authors: Guo-Ruey Tsai
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/s9e9sr

碩士 === 崑山科技大學 === 電子工程研究所 === 96 === This paper proposes a hardware/software co-design approach to reconfigure a RISC processor which is used to implement a digital filter. According to practical requirement, the application specified instruction set can be tuned, and then the processor hardware can be reconfigured to achieve higher area efficiency. With compact instruction set and single clock execution speed, the FIR design affords high speed performance for both MAC parallel procession and those HDL programs which need sequential procession. The proposed FIR filter only consumes 5 % of Xilinx XC3S500E Spartan-3E FPGA chip area. With high area efficiency, the digital filter is not only for single channel signal processing, but also for multi-channel signal processings with same sampling frequency, which is designed by time-sharing software engineering. When the sampling frequencies of multi-channel signal are inconsistent, we can build into several different FIRs or DSP modules in a single FPGA to increase the system performance and design flexibility. Further, we can increase FIR tapping number by cascading model, or upgrading FIR sampling speed by parallel model.