Hardware/Software Co-Design FPGA-based Digital Signal Processor with High Area Efficiency
碩士 === 崑山科技大學 === 電子工程研究所 === 96 === This paper proposes a hardware/software co-design approach to reconfigure a RISC processor which is used to implement a digital filter. According to practical requirement, the application specified instruction set can be tuned, and then the processor hardware can...
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/s9e9sr |
id |
ndltd-TW-096KSUT5428068 |
---|---|
record_format |
oai_dc |
spelling |
ndltd-TW-096KSUT54280682019-05-15T20:33:46Z http://ndltd.ncl.edu.tw/handle/s9e9sr Hardware/Software Co-Design FPGA-based Digital Signal Processor with High Area Efficiency 軟硬體共同設計演算法實現高面積效率的數位處理器 Yu-Kai Tsai 蔡玉凱 碩士 崑山科技大學 電子工程研究所 96 This paper proposes a hardware/software co-design approach to reconfigure a RISC processor which is used to implement a digital filter. According to practical requirement, the application specified instruction set can be tuned, and then the processor hardware can be reconfigured to achieve higher area efficiency. With compact instruction set and single clock execution speed, the FIR design affords high speed performance for both MAC parallel procession and those HDL programs which need sequential procession. The proposed FIR filter only consumes 5 % of Xilinx XC3S500E Spartan-3E FPGA chip area. With high area efficiency, the digital filter is not only for single channel signal processing, but also for multi-channel signal processings with same sampling frequency, which is designed by time-sharing software engineering. When the sampling frequencies of multi-channel signal are inconsistent, we can build into several different FIRs or DSP modules in a single FPGA to increase the system performance and design flexibility. Further, we can increase FIR tapping number by cascading model, or upgrading FIR sampling speed by parallel model. Guo-Ruey Tsai 蔡國瑞 2008 學位論文 ; thesis 50 zh-TW |
collection |
NDLTD |
language |
zh-TW |
format |
Others
|
sources |
NDLTD |
description |
碩士 === 崑山科技大學 === 電子工程研究所 === 96 === This paper proposes a hardware/software co-design approach to reconfigure a RISC processor which is used to implement a digital filter. According to practical requirement, the application specified instruction set can be tuned, and then the processor hardware can be reconfigured to achieve higher area efficiency. With compact instruction set and single clock execution speed, the FIR design affords high speed performance for both MAC parallel procession and those HDL programs which need sequential procession.
The proposed FIR filter only consumes 5 % of Xilinx XC3S500E Spartan-3E FPGA chip area. With high area efficiency, the digital filter is not only for single channel signal processing, but also for multi-channel signal processings with same sampling frequency, which is designed by time-sharing software engineering. When the sampling frequencies of multi-channel signal are inconsistent, we can build into several different FIRs or DSP modules in a single FPGA to increase the system performance and design flexibility. Further, we can increase FIR tapping number by cascading model, or upgrading FIR sampling speed by parallel model.
|
author2 |
Guo-Ruey Tsai |
author_facet |
Guo-Ruey Tsai Yu-Kai Tsai 蔡玉凱 |
author |
Yu-Kai Tsai 蔡玉凱 |
spellingShingle |
Yu-Kai Tsai 蔡玉凱 Hardware/Software Co-Design FPGA-based Digital Signal Processor with High Area Efficiency |
author_sort |
Yu-Kai Tsai |
title |
Hardware/Software Co-Design FPGA-based Digital Signal Processor with High Area Efficiency |
title_short |
Hardware/Software Co-Design FPGA-based Digital Signal Processor with High Area Efficiency |
title_full |
Hardware/Software Co-Design FPGA-based Digital Signal Processor with High Area Efficiency |
title_fullStr |
Hardware/Software Co-Design FPGA-based Digital Signal Processor with High Area Efficiency |
title_full_unstemmed |
Hardware/Software Co-Design FPGA-based Digital Signal Processor with High Area Efficiency |
title_sort |
hardware/software co-design fpga-based digital signal processor with high area efficiency |
publishDate |
2008 |
url |
http://ndltd.ncl.edu.tw/handle/s9e9sr |
work_keys_str_mv |
AT yukaitsai hardwaresoftwarecodesignfpgabaseddigitalsignalprocessorwithhighareaefficiency AT càiyùkǎi hardwaresoftwarecodesignfpgabaseddigitalsignalprocessorwithhighareaefficiency AT yukaitsai ruǎnyìngtǐgòngtóngshèjìyǎnsuànfǎshíxiàngāomiànjīxiàolǜdeshùwèichùlǐqì AT càiyùkǎi ruǎnyìngtǐgòngtóngshèjìyǎnsuànfǎshíxiàngāomiànjīxiàolǜdeshùwèichùlǐqì |
_version_ |
1719100917592096768 |