Multiple analog CCD signal processing and frame division by FPGA-based FIFO design
碩士 === 崑山科技大學 === 電子工程研究所 === 96 === This article takes advantages of re-configurability, built in block RAM and embedded processor from a FPGA chip, to design a FIFO_based stream video signal procession accelerator IP. The accelerator IP can be packed into a general propose stream video co-process...
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/tju7v5 |