| Summary: | 碩士 === 國立中興大學 === 資訊科學與工程學系 === 96 === Network-on-chip (NoC) communication fabrics will be increasingly used in many large multi-core system-on-chip designs in the near future. A relevant challenge that arises from this trend is that the test costs associated with NoC infrastructures may account for a significant part of the total test cost. Structural tests have deficiencies in terms of hardware overhead and test application time which is bypassed by functional tests. In this paper, we analyzed the functional fault models and present a new test approach for testing such NoC architectures. The fault models used are specific to router switch, network interface, and channels between them. The novelty of our approach lies in the using the regularity of the 2D-Mseh NoC structures to concurrently transport test packet without congestions. This mechanism reduced the test time and, implicitly, the test cost.
Experimental results show the efficiency that it is able to reduce the test time significantly and 100% router switch port fault coverage, as compared with the other literatures.
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