Designs and analyses of low complexity pulse triggered flip-flops

• Main Authors: Wei-Rong Ciou, 邱薇蓉
• Other Authors: 黃穎聰
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/88912617312969211137

碩士 === 國立中興大學 === 電機工程學系所 === 96 === In this thesis, we proposed two novel pulse-triggered flip-flop designs for functional versatility. The first circuit is a dual-mode flip-flop, i.e. single- and double-edge triggered modes. A dual-mode pulse generator using pass transistor logic (PTL) is derived first. Both threshold voltage loss and poor driving capability problems common in PTL design are successfully resolved while the circuit simplicity is kept. Combining the pulse generator design with a level sensitive latch leads to a dual-mode pulse-triggered flip-flop (DMP-FF) design. Extensive performance comparisons, including with one programmable FF design for FPGAs and with three other single mode pulse-triggered FF designs and, are conducted. The proposed design, with a much smaller layout area, edges over the programmable FF design significantly in speed and power consumption. The proposed design, bearing similar circuit complexity plus the advantage of dual mode operations, also performs equally well as other single mode designs do in various AC parameters and power consumption. Besed on the same circuit technique, another low complexity pulse generator design for programmable pulse-triggered flip-flop using two AND logic tree with disable function (PPT-FF) is next presented. With the minumin number of transistors, this design successfully incorporates 3 triggering modes and disable function (clock gating). Both circuit complexity and loading capacitance of clock tree system can thus be reduced. Simulation results are given to show its performance edges. The comparisons of all data are conducted using post-layout simulations in TSMC 0.18μm CMOS process technology. Simulation results also indicate that the DMP-FF can rival or even outperform other single- or dual-mode designs in various performance indexes. The PPT-FF results have demonstrated its ability to achieve up to 2 and 6 times power consumption and power-delay-product saving compared with master-slave based design.