A 4-Bit 1GSPS Flash ADC with Step-Shifted Background Calibration
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === A 4-bit flash ADC with step-shifted background calibration method is proposed in this thesis. This system would increase one comparator, switches for resistor ladder and use the random phase generator to generate shifted and non-shifted states. For the same c...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85125639040706939529 |