Design of a Digital Pulse-Width Locked Loop
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 96 === In recent years, semiconductor integrated circuits exhibit significant performance improvements as the operating frequency increases. However, it is not easy to ensure the signal integrity, especially when the circuit is complicated and operated in high clock...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/56512640555104834139 |