Design of a Pipelined Analog-to-Digital Converter
碩士 === 國立暨南國際大學 === 電機工程學系 === 96 === In this thesis, we design a 10-bit 50MHz pipelined analog-to-digital converter with TSMC 0.35um 2P4M mixed signal process technology at 3.3V power supply voltage. The ADC architecture is nine stage pipelined ADC in this design. In formal we adopt eight conversio...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00931899771435380082 |