| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 96 === In this thesis, we design a 10-bit 50MHz pipelined analog-to-digital converter with TSMC 0.35um 2P4M mixed signal process technology at 3.3V power supply voltage. The ADC architecture is nine stage pipelined ADC in this design. In formal we adopt eight conversion stage 1.5-bit per stage technology and a 2-bit flash ADC in the last stage. We adopt switch-capacitor circuit to design the sample and hold circuit (S/H) and the multiplying DAC (MDAC). In order to reduce the nonlinearity of input switch, the bootstrapped switch structure is used to implement the switches of S/H input. Finally, we can get accurate 10-bit digital codes by using digital error correction circuit. Meanwhile, in order to decrease noise affection, the whole circuit is designed by fully differential structure.
According to Hspice simulation result, the designed pipelined ADC can operate at 50MHz. The Signal-to-Noise and Distortion Ratio is 57.94dB when the input frequency is 1MHz and effective number of bit is 9.33-bit. The power dissipation is 174mW. The chip layout area is 2487.9um*2179.7um.
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