Design of a Pipelined Analog-to-Digital Converter
碩士 === 國立暨南國際大學 === 電機工程學系 === 96 === In this thesis, we design a 10-bit 50MHz pipelined analog-to-digital converter with TSMC 0.35um 2P4M mixed signal process technology at 3.3V power supply voltage. The ADC architecture is nine stage pipelined ADC in this design. In formal we adopt eight conversio...
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ndltd-TW-096NCNU04420372015-10-13T13:47:50Z http://ndltd.ncl.edu.tw/handle/00931899771435380082 Design of a Pipelined Analog-to-Digital Converter 管線式類比數位轉換器設計 Cheng-Che Tang 唐正哲 碩士 國立暨南國際大學 電機工程學系 96 In this thesis, we design a 10-bit 50MHz pipelined analog-to-digital converter with TSMC 0.35um 2P4M mixed signal process technology at 3.3V power supply voltage. The ADC architecture is nine stage pipelined ADC in this design. In formal we adopt eight conversion stage 1.5-bit per stage technology and a 2-bit flash ADC in the last stage. We adopt switch-capacitor circuit to design the sample and hold circuit (S/H) and the multiplying DAC (MDAC). In order to reduce the nonlinearity of input switch, the bootstrapped switch structure is used to implement the switches of S/H input. Finally, we can get accurate 10-bit digital codes by using digital error correction circuit. Meanwhile, in order to decrease noise affection, the whole circuit is designed by fully differential structure. According to Hspice simulation result, the designed pipelined ADC can operate at 50MHz. The Signal-to-Noise and Distortion Ratio is 57.94dB when the input frequency is 1MHz and effective number of bit is 9.33-bit. The power dissipation is 174mW. The chip layout area is 2487.9um*2179.7um. Chih-Wen Lu 盧志文 2008 學位論文 ; thesis 149 zh-TW |
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碩士 === 國立暨南國際大學 === 電機工程學系 === 96 === In this thesis, we design a 10-bit 50MHz pipelined analog-to-digital converter with TSMC 0.35um 2P4M mixed signal process technology at 3.3V power supply voltage. The ADC architecture is nine stage pipelined ADC in this design. In formal we adopt eight conversion stage 1.5-bit per stage technology and a 2-bit flash ADC in the last stage. We adopt switch-capacitor circuit to design the sample and hold circuit (S/H) and the multiplying DAC (MDAC). In order to reduce the nonlinearity of input switch, the bootstrapped switch structure is used to implement the switches of S/H input. Finally, we can get accurate 10-bit digital codes by using digital error correction circuit. Meanwhile, in order to decrease noise affection, the whole circuit is designed by fully differential structure.
According to Hspice simulation result, the designed pipelined ADC can operate at 50MHz. The Signal-to-Noise and Distortion Ratio is 57.94dB when the input frequency is 1MHz and effective number of bit is 9.33-bit. The power dissipation is 174mW. The chip layout area is 2487.9um*2179.7um.
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Chih-Wen Lu |
author_facet |
Chih-Wen Lu Cheng-Che Tang 唐正哲 |
author |
Cheng-Che Tang 唐正哲 |
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Cheng-Che Tang 唐正哲 Design of a Pipelined Analog-to-Digital Converter |
author_sort |
Cheng-Che Tang |
title |
Design of a Pipelined Analog-to-Digital Converter |
title_short |
Design of a Pipelined Analog-to-Digital Converter |
title_full |
Design of a Pipelined Analog-to-Digital Converter |
title_fullStr |
Design of a Pipelined Analog-to-Digital Converter |
title_full_unstemmed |
Design of a Pipelined Analog-to-Digital Converter |
title_sort |
design of a pipelined analog-to-digital converter |
publishDate |
2008 |
url |
http://ndltd.ncl.edu.tw/handle/00931899771435380082 |
work_keys_str_mv |
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