| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 96 === In this study, we proposed a digital signal processor which supports dual logarithm based and use its specific instruction set to implement the speech recognition algorithm. We use hardware-software co-design methodology to optimize the processor architecture and instruction set. In terms of architecture, the processor supports dual logarithm based operator. If the processor doesn’t support logarithm operator, we must use other method instead logarithm operator when using it. But it cost a lot of time and its resolution is not enough precise to we need. So we design a processor which supports logarithm operator to evaluate logarithm quickly and get more precise resolution. Finally, the total gate count of this processor is about 550,000 synthesized and estimated with TSMC 0.13 um standard library. The maximum clock frequency of this processor is about 50MHz.
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