Wire Length Driven Flip-Chip Pin-Out Designation by Range Constrained Pin-Block Floorplanning in Package-Board Codesign
碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 96 === With the advanced fabrication technique developing rapidly, more and more circuits could be integrated in a single chip. This trend will cause the complication in package designs and signal interconnection. However, the typical peripheral wire-bond design ma...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/00116203163626550252 |