Performance-Driven Obstacle-Avoiding Rectilinear Steiner Tree Construction
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 96 === With technology scaling, interconnect delay has dominated circuit delay. Mean-while, modern System on Chip (SOC) design contains many obstacles such as IP cores, macro blocks, and pre-routed nets within the routing region. Most previous works on obstacle-avoid...
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| Format: | Others |
| Language: | en_US |
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2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/15336727251669665982 |