Self-Timed Torus Interconnection Network with one-of-five encoding
碩士 === 國立交通大學 === 資訊科學與工程研究所 === 96 === Because of the slow signal propagation caused by the high wire loads and resistance, the interconnection of SoC cannot be satisfied by the use of a shared bus. A common method of substitution is using unidirectional, point-to-point connections and multiplexers...
Main Authors: | Man-Chen Huang, 黃曼珍 |
---|---|
Other Authors: | Chang-Jiu Chen |
Format: | Others |
Language: | en_US |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/46668257127202828942 |
Similar Items
-
Asynchronous Bi-direction Interconnection Network using Torus Topology
by: Tsai, Chia-Cheng, et al.
Published: (2009) -
The design of a router for 2D torus interconnection networks
by: ZHANG,JIN-YUAN, et al.
Published: (1991) -
Reliable low latency I/O in torus-based interconnection networks
by: Azeez, Babatunde
Published: (2007) -
Torus–Connected Cycles: A Simple and Scalable Topology for Interconnection Networks
by: Bossard Antoine, et al.
Published: (2015-12-01) -
Visualizing the Topology and Data Traffic of Multi-Dimensional Torus Interconnect Networks
by: Shenghui Cheng, et al.
Published: (2018-01-01)