Reducing Code Size in Java JIT Compilers for 32bit-16bit Mixed Instruction Set Architectures

• Main Authors: Li-Jyun Lyu, 呂禮君
• Other Authors: Wuu Yang
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/17804420283987662743

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 96 === In recent years, because the market of embedded systems develops quickly, the process speed of embedded systems had rapidly grown. As the processors become faster and faster, the bottleneck of program execution shifts to the communication between CPU and the main memory. The main reason is the increasing gap between CPU speed and memory speed. Reducing code size may potentially reduce the number of memory accesses (by increasing cache hit ratio) and becomes an effective method to improve CPU performance. For this reason, new CPU architectures provide both 16-bit and 32-bit instructions. We developed a new method that can generate a mixture of 16-bit and 32-bit instructions. This method is implemented and tested in a Java just-in-time compiler of a Java virtual machine for the Andes platform. Our experiment shows that the code size can be reduced 10% at very little extra overhead (only 0.13%). The performance improvement for a long-running program can be quite significant.