Ultra Low-Power and High-Performance 32-Bit Embedded Processor with JPEG Decoder System

碩士 === 國立交通大學 === 電子工程系所 === 96 === This thesis presents the research result of an ultra low-power and high-performance 32-bit embedded processor with JPEG decoder system. This processor is named ACARM7 (ACademic ARM7). The ISA (Instruction Set Architecture) of ACARM7 adopts the ARM V4 architecture....

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Bibliographic Details
Main Authors: Je-Ling Hsu, 許哲霖
Other Authors: Juinn-Dar Huang
Format: Others
Language:en_US
Published: 2007
Online Access:http://ndltd.ncl.edu.tw/handle/33455761081632868123