The Study of Co-Planar Type Poly-Si EEPROM with Nano-Scale
碩士 === 國立交通大學 === 電子工程系所 === 96 === Planar Twin Cell TFT of NVM memory can be fabricated under 600C degree，Gate connecting the two TFT becomes the floating gate。 The larger TFT connecting the drain and source becomes the control gate。Using this type of device structure， we can save huge cost。Nanowir...
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| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/76554558078292995763 |