Phase-Locked Loop Design with Double Sampling Phase Detector
碩士 === 國立交通大學 === 電子工程系所 === 96 === In this thesis, a charge-pump phase-locked loop (PLL) design with double sampling phase detector (DSPD) is proposed. By using the double sampling phase detector, the PLL loop bandwidth is doubled to obtain the fast settling time and meanwhile shift the reference s...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/49920405221876604204 |