Phase-Locked Loop Design with Double Sampling Phase Detector

• Main Authors: Guo-Jue Huang, 黃國爵
• Other Authors: Kuei-Ann Wen
• Format: Others
• Language: en_US
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/49920405221876604204

碩士 === 國立交通大學 === 電子工程系所 === 96 === In this thesis, a charge-pump phase-locked loop (PLL) design with double sampling phase detector (DSPD) is proposed. By using the double sampling phase detector, the PLL loop bandwidth is doubled to obtain the fast settling time and meanwhile shift the reference spur to higher frequency to suppress the reference spur. For system analysis, a third-order charge-pump PLL with DSPD linear model is developed. Verilog-AMS charge-pump PLL timing models with DSPD and conventional phase detector (PD) are developed to verify the fast settling time and reference spur suppression. A 2.304 GHz/ 2.88GHz charge-pump PLL with two operation modes, DSPD mode and conventional PD mode, is designed. From the simulation results, the settling time is reduced 50% in 30ppm frequency accuracy and the reference spur is suppressed 16dB.