A Low Power Reconfigurable FFT Processor with Minimum Switching Activity
碩士 === 國立交通大學 === 電子工程系所 === 96 === In this thesis, a low power reconfigurable FFT processor is proposed. The memory based FFT can be configured as from 64-point to 8192-point. Besides, a modified coefficient ordering method with minimum switching activity is proposed for low power design. The switc...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/90034525823938383057 |