| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 96 === As the improvement of semiconductor process and technology, the device size of CMOS ICs has been scaled down and more complicated functions are integrated into a single chip. The potential destructive nature of ESD in CMOS ICs becomes serious and the design of ESD protection circuits becomes more challenging in scaled-down CMOS process. Therefore ESD protection has become an important reliability issue in CMOS IC products.
System-level ESD is an increasingly important reliability issue in CMOS IC products. It has been also reported that reliability issues still exist in CMOS ICs under system-level ESD tests, even though they have passed component-level ESD specifications. In order to meet high electromagnetic compatibility (EMC) regulations, the microelectronic products are required to evaluate system performance under reliability test standard of system-level ESD tests. In the system-level ESD test standard of IEC 61000-4-2, the microelectronic products are required to sustain the ESD voltage of ±8kV (±15kV) under contact-discharge (air-discharge) test mode to achieve the immunity requirement of “level 4”. The experimental results have confirmed that the power and ground lines of microelectronic products no longer maintain the normal operating voltage under system-level ESD tests, but underdamped sinusoidal waveforms instead. Furthermore, the transient noise under system-level ESD tests can cause system into locked state, system frozed state, transient-induced latch-up, or even hardware damage. In traditional solutions, extra discrete components are added on PCB to suppress system-level ESD events in microelectronic products. Therefore, the chip-level solutions to meet high system-level ESD specification for microelectronic products are strongly requested by IC industry.
In chapter 2, two transient detection circuits have been designed and investigated to detect the fast electrical transients on the power line (VDD) and ground line (VSS) under system-level ESD tests. In chapter 3, the proposed on-chip transient detection circuits have been fabricated in a 0.18-μm CMOS process with 3.3-V devices. The circuit performance of the circuits has been evaluated by transient induced latchup (TLU) tests, system-level ESD tests, and EFT tests. It has been confirmed that the transient detection circuits can detect and memorize the occurrence of the positive (negative) fast electrical transients on the power and ground lines of CMOS ICs.
Evaluation on the board-level noise filter network to reduce the ESD energy coupling into the DUT under system-level ESD tests is investigated in chapter 4. Different types of board-level noise filters, including capacitor filter, LC-like (2nd-order) filter, π-section (3rd-order) filter, etc., have been evaluated to change the detection range of the proposed on-chip transient detection circuits.
In chapter 5, a novel on-chip transient-to-digital converter composed of four transient detection circuits and four different RC filters has been successfully designed and verified in a 0.18-μm CMOS process with 3.3-V devices. The output thermometer digital codes of the proposed on-chip transient-to-digital converter correspond to different positive/negative ESD voltages under system-level ESD tests. These output digital codes can be used as the firmware index to execute different auto-recovery procedures in microelectronic systems. Therefore, the system with auto-detection function can detect the transient noise and then automatically reset itself to achieve the “Class B” specification defined in the IEC 61000-4-2 standard.
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