SAW Based Half Rate Clock Recovery for High Speed Serial Data Transmission
碩士 === 國立交通大學 === 電信工程系所 === 96 === The purpose of this thesis is to implement a clock and data recovery (CDR) for Stratum 3. The bit rate is 1.244Gb/s for OC-24 by using TSMC 0.18um CMOS process. The voltage controlled SAW Oscillator (VCSO) is designed for low phase noise application. The low pass...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/32295505920248976616 |