Design of a Clock Recovery Circuit for the 32~96KHz SPDIF/AES Receiver
碩士 === 國立交通大學 === 電機與控制工程系所 === 96 === In communication systems, the received signals are usually contaminated by the channel noise and distorted by the finite channel bandwidth. As a result, they often carry a lot of jitter. At the receiver end, we need a clock recovery circuit to recovery a low ji...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/12711423263204265864 |