On Minimizing Substrate Noise and Meeting Symmetry Constraint in Mixed-Signal SoC Floorplan Design
碩士 === 國立交通大學 === 電機學院碩士在職專班電機與控制組 === 96 === In recent years, in order to handle substrate noise and process variation in high-end mixed-signal circuit, analog circuits are often required placement symmetrically to the axis, and high noise digital circuits need to far aware form noise interference...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/50083128610336677798 |