The Strategy of Overlay Error Control in Semiconductor Lithography
碩士 === 國立交通大學 === 工學院碩士在職專班半導體材料與製程設備組 === 96 === This paper aimed to minimize the overlay error model by optimizing process factor and increasing the alignment accuracy. We designed the alignment sampling strategies including the number of sampling points and sampling position to increase the align...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/3n82v9 |