The Strategy of Overlay Error Control in Semiconductor Lithography

• Main Authors: Kuo-Yu Wu, 吳國裕
• Other Authors: Edward Yi Chang
• Format: Others
• Language: zh-TW
• Published: 2008
• Online Access: http://ndltd.ncl.edu.tw/handle/3n82v9

碩士 === 國立交通大學 === 工學院碩士在職專班半導體材料與製程設備組 === 96 === This paper aimed to minimize the overlay error model by optimizing process factor and increasing the alignment accuracy. We designed the alignment sampling strategies including the number of sampling points and sampling position to increase the alignment accuracy, then, the overlay errors can be corrected by exposure stage and the lens element of equipment. Furthermore, we studied the entire process factors that were overlay related, and optimized the process recipe by DOE methods. We compared the proposed alignment sampling strategy with alternative sampling strategies including the existing alignment strategies based on the model adequacy of alignment and the overlay residual errors. The proposed model and alignment sampling strategy are validated by empirical studies conducted in a fab. From the experiment result we got an excellent overlay improvement .The results demonstrated the practical viability of the proposed approach.