The Strategy of Overlay Error Control in Semiconductor Lithography
碩士 === 國立交通大學 === 工學院碩士在職專班半導體材料與製程設備組 === 96 === This paper aimed to minimize the overlay error model by optimizing process factor and increasing the alignment accuracy. We designed the alignment sampling strategies including the number of sampling points and sampling position to increase the align...
Main Authors: | Kuo-Yu Wu, 吳國裕 |
---|---|
Other Authors: | Edward Yi Chang |
Format: | Others |
Language: | zh-TW |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/3n82v9 |
Similar Items
-
The Study of Semiconductor Lithography Overlay Control
by: Chang, Po-Chung, et al.
Published: (2012) -
Overlay Error Control of Lithography Process
by: Cha, Meng-Hsun, et al.
Published: (2011) -
Lithography Overlay Error Analysis of LCD Application
by: Chen-Yu Chiang, et al.
Published: (2005) -
Applying Virtual Metrology to the Control of Overlay Error in Lithography Process
by: Chien-Hui Li, et al.
Published: (2009) -
Overlay Control for Lithography Process
by: Tsu-Chiang Lin, et al.
Published: (2005)