Asymmetric-LDD MOS of SPDT Switch for Ultra Wideband 3.1~10.6GHz

• Main Authors: Pei-Yu Lee, 李佩諭
• Other Authors: Albert Chin
• Format: Others
• Language: en_US
• Published: 2007
• Online Access: http://ndltd.ncl.edu.tw/handle/9v652z

碩士 === 國立交通大學 === 電機學院微電子奈米科技產業專班 === 96 === The topic of research is T/R switch for ultra-wideband 3.1-10.6GHz application, it was designed by series-shunt topology. The circuit is fabricated in 0.18μm CMOS process. The higher drain breakdown voltage of asymmetric-LDD MOS transistor is used for the transmitter path. The key point is the larger bias on the transmitter path to improve the power linearity. Besides, the body-floating technique is also used to improve the linearity and power-handling capability of T/R switch. The chip size is 0.325mm2. The effective area is 0.11mm2. The measured maximum insertion loss is 1.8dB and 4.1dB for transmitter and receiver respectively. The P1dB compression point is 28.7dBm. However, the higher insertion loss is on the RX mode. Therefore the circuit has been redesigned in order to decrease the loss. According to the simulated result, the maximum insertion loss is 0.94dB and 1.29dB for transmitter and receiver respectively. Besides, the P1dB compression point can achieve 30.1dBm. The layout area is 0.21mm2. The effective area is only 0.055mm2.