A 2.5GHz Fast Locking Self-Calibration Phase-Locked Loop Designed in 90nm Process
碩士 === 國立中央大學 === 電機工程研究所 === 96 === The performance and speed of VLSI circuits grew up with scale-down process, and now the chip changes to integrate SOC. There is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. The different phase of operate...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99784553631950505119 |