| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 96 === The performance and speed of VLSI circuits grew up with scale-down process, and now the chip changes to integrate SOC. There is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. The different phase of operate clock that caused to output data error in integrate system. Hence, it needs Phase-Locked Loop (PLL) for decreasing phase error that make the clock phase is corresponding in order to decrease output data error in sub-circuit of integrate system.
In this thesis, a fast locking self-calibration PLL is proposed. It can produce 2.5GHz output frequency and eight different phases. Multi-band scheme can decrease the gain (Kvco) of voltage controlled oscillator. That can achieve the low jitter of output signal in the PLL circuit. Self-calibration technology is used to lock the frequency of 2.5GHz at any process variation. Generally speaking, there are two kinds of self-calibration, the open-loop calibration and the close-loop calibration. However, those self-calibration methods spend the long time for frequency locked. In order to achieve the fast locking in the close-loop calibration circuit, the digital control skill of calibration method is used to improve the locking time.
We use the CMOS 90nm 1P9M process with supplying 1V voltage in proposed PLL. The reference input frequency is 312.5MHz and the output frequency is 2.5GHz. The period jitter of output frequency is 1.83ps (pk-pk) .If the input signal of the PLL had 20ps jitter (pk-pk), the period jitter of output frequency was 22.1ps (pk-pk).The power consumption of the proposed PLL is 26mW at 2.5GHz and the Locking time of the PLL is 450ns. The core area is 0.09mm^2.
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