A 2.5GHz Fast Locking Self-Calibration Phase-Locked Loop Designed in 90nm Process
碩士 === 國立中央大學 === 電機工程研究所 === 96 === The performance and speed of VLSI circuits grew up with scale-down process, and now the chip changes to integrate SOC. There is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. The different phase of operate...
Main Authors: | Yu-Fen Lin, 林鈺芬 |
---|---|
Other Authors: | Kuo-Hsing Cheng |
Format: | Others |
Language: | zh-TW |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/99784553631950505119 |
Similar Items
-
Delay-Locked Loops with fast lock and phase error calibration
by: Chun Yi Kuo, et al.
Published: (2012) -
A 5GHz Ultra-low Power and Fast Locking CMOS Phase-Locked Loop
by: Yue-Fang Kuo, et al.
Published: (2005) -
Design and Implementation of 1-Volt GHz and Fast-Locking Phase-Locked Loop
by: Shu-Chang Kuo, et al.
Published: (2004) -
A Digitally-Calibrated 65GHz Phase-Locked Loop
by: Jia-Hao Wu, et al.
Published: (2007) -
A 100MHz-1GHz Adaptive Bandwidth Phase-locked Loop Designed in 90nm Process
by: Kai-Fei Chang, et al.
Published: (2006)