An Improved Pulse Shrinking Delay Element for Clock Jitter Measurement
碩士 === 國立中央大學 === 電機工程研究所 === 96 === As the improvement of semiconductor technology, the current trend of VLSI circuit is System-on-Chip (SOC). When many systems were integrated into a chip, the system synchronization clock signal must be accurate. We usually choose Phase-Locked Loop (PLL) or Delay-...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/09382124093328045250 |