| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 96 === As the improvement of semiconductor technology, the current trend of VLSI circuit is System-on-Chip (SOC). When many systems were integrated into a chip, the system synchronization clock signal must be accurate. We usually choose Phase-Locked Loop (PLL) or Delay-Locked Loop (DLL) as the reference clock generator. However, the jitter characteristic of the PLLs or DLLs is the most important parameter. In the past, the jitter was measured by the external equipment. But, with the increased operating frequency, it has a higher cost on jitter measuring by external equipments. Moreover, sometimes probes of external equipments will induce noise, then the measurement result is disturbed. In view the problem, the built-in jitter measurement circuit is adapted to the PLLs.
In this thesis, an improved pulse shrinking delay element for clock jitter measurement is proposed. The traditional cyclic CMOS time-to-digital converter circuit [1] was changed the size of inverters to complete pulse shrink. We use two path with differential rising time and falling time to achieve pulse shrink. In order to make the measurable circuit have high accuracy, the compensated circuit is added to compensate the voltage and process variation.
The proposed circuit is designed in CMOS 0.18um 1P6M process. The operation voltage is 1.8V in the circuit. The reference frequency is 1GHz and the resolution of measurement circuit is 5ps. The power consumption is 1.7mW
at 1GHz. Area with I/O pad in the chip is 753um × 592um, and the area of core circuit is 108um × 59um.
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