Characterization of Gate Leakage Current and Channel Length of Nanometer-scaled MOSFETs

博士 === 國立清華大學 === 電子工程研究所 === 96 === This dissertation contains the DC characterization of nanometer-scaled metal-oxide-semiconductor field-effect-transistors. Two major achievements are obtained: the establishment of a gate leakage current model and accurate parameter extraction from the drain to s...

Full description

Bibliographic Details
Main Authors: Chun-Chia Yeh, 葉俊佳
Other Authors: J. Gong
Format: Others
Language:en_US
Published: 2007
Online Access:http://ndltd.ncl.edu.tw/handle/79489110569213786088
Description
Summary:博士 === 國立清華大學 === 電子工程研究所 === 96 === This dissertation contains the DC characterization of nanometer-scaled metal-oxide-semiconductor field-effect-transistors. Two major achievements are obtained: the establishment of a gate leakage current model and accurate parameter extraction from the drain to source current-voltage relations. In first achievement, a mathematical method of modeling the gate leakage current IG is presented. Both the shallow trench isolation effect and the source drain extension effect on IG are included. With suitably chosen transistor dimensions the parameter extraction can be performed with the devices’ drawn size, the troublesome effective device length and width is not necessary in this model. The extracted parameters were used to predict IG of devices with other different dimensions. Transistors fabricated with 90nm and 65nm technologies were examined. The extracted parameters and their temperature dependence were used to predict IG of devices with other dimensions, excellent accuracy is verified. In second achievement, the concepts of shift-and-ratio (S&R) method are used. According to this foundation, we point out some different viewpoints that include a drain current corrected by gate leakage current, surface potential, velocity saturation model, and diffusion current portion of the drain current. After considering these factors which relate to the effective channel length (Leff) and source/drain series resistance (RSD) and we can get eight nonlinear equations. Then, iteration method is applied to solve these equations to obtain accurate RSD and Leff. Because RSD and Leff are two inseparable device parameters, therefore, the iterated steps can obtain more accurate parameters simultaneously. The results differ from that obtained from the original S&R method; both our outcomes are function of VGS. Furthermore, our algorithm only needs to measurement IDS-VGS curve before calculating the results. Therefore, this proposed method can be easily implemented in MOSFET’s modeling.