A Supply-Noise-Insensitive PLL Design with A Supply Regulated VCO
碩士 === 國立清華大學 === 電機工程學系 === 96 === Phase locked-loops (PLLs) are widely used in digital systems to generate well-timed clocks. Clock timing jitter is one of the most significant issues since any timing uncertainty limits the speed of digital systems. Scaling trends will shrink supply voltage and in...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2007
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/77081724708564018658 |