An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager
碩士 === 國立清華大學 === 通訊工程研究所 === 96 ===
Main Authors: | , |
---|---|
Other Authors: | |
Format: | Others |
Language: | zh-TW |
Published: |
2008
|
Online Access: | http://ndltd.ncl.edu.tw/handle/42039276570268775906 |