An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager

An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager

碩士 === 國立清華大學 === 通訊工程研究所 === 96 ===

Bibliographic Details
Main Authors:	Chu-Sheng Ku, 古竹生
Other Authors:	Cheng-Shang Chang
Format:	Others
Language:	zh-TW
Published:	2008
Online Access:	http://ndltd.ncl.edu.tw/handle/42039276570268775906

Description
Summary:	碩士 === 國立清華大學 === 通訊工程研究所 === 96 ===