An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager

An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager

碩士 === 國立清華大學 === 通訊工程研究所 === 96 ===

Bibliographic Details
Main Authors: Chu-Sheng Ku, 古竹生
Other Authors: Cheng-Shang Chang
Format: Others
Language:zh-TW
Published: 2008
Online Access:http://ndltd.ncl.edu.tw/handle/42039276570268775906
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spelling ndltd-TW-096NTHU56500222015-11-27T04:04:16Z http://ndltd.ncl.edu.tw/handle/42039276570268775906 An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager 以FPGA實作40Gbps超高速先進先出佇列–緩衝記憶體管理 Chu-Sheng Ku 古竹生 碩士 國立清華大學 通訊工程研究所 96 Cheng-Shang Chang 張正尚 2008 學位論文 ; thesis 40 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立清華大學 === 通訊工程研究所 === 96 ===
author2 Cheng-Shang Chang
author_facet Cheng-Shang Chang
Chu-Sheng Ku
古竹生
author Chu-Sheng Ku
古竹生
spellingShingle Chu-Sheng Ku
古竹生
An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager
author_sort Chu-Sheng Ku
title An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager
title_short An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager
title_full An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager
title_fullStr An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager
title_full_unstemmed An FPGA Implementation of a 40Gbps Ultra High Speed FIFO Queue - Buffer Manager
title_sort fpga implementation of a 40gbps ultra high speed fifo queue - buffer manager
publishDate 2008
url http://ndltd.ncl.edu.tw/handle/42039276570268775906
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AT gǔzhúshēng yǐfpgashízuò40gbpschāogāosùxiānjìnxiānchūzhùlièhuǎnchōngjìyìtǐguǎnlǐ
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AT gǔzhúshēng fpgaimplementationofa40gbpsultrahighspeedfifoqueuebuffermanager
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