Clock and Data Recovery Circuit with Improved Half-Rate Linear Phase Detector
碩士 === 臺灣大學 === 電子工程學研究所 === 96 === In this thesis, we will introduce general clock and data recovery (CDR) circuit architectures and describe the building blocks including phase detector, voltage control oscillator, and frequency detector. And the operation principles of each building block will be...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2007
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| Online Access: | http://ndltd.ncl.edu.tw/handle/28681929076217453132 |