Automatic Partitioner for Distributed Parallel Verification Simulation
碩士 === 國立臺灣大學 === 電子工程學研究所 === 96 === Due to the increasing complexity of circuit design, the verification through simulation has become a bottleneck of the IC design process. Distributed parallel simulation seems to be one of the best ways to solve the problem. In order to distribute the workload o...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2008
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| Online Access: | http://ndltd.ncl.edu.tw/handle/78803909177361658907 |